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| TV Mixer-Oscillator-PLL for 1.1 GHz TUA 6010X 1 1.1 Overview Features * Smallest possible lock-in time; no asynchronous divider stage * 1-chip system for MPU control (I2C Bus) * Fast I2C Bus mode possible * 4 programmable chip addresses P-DSO-28-1 * Short pull-in time for quick channel switch-over and optimized loop stability * 3 high-current switch outputs * 2 TTL inputs * 5-level A/D converter * Lock-in flag * Power-down flag * Few external components * Frequency and amplitude-stable balanced oscillator for the VHF, HYPER and UHF frequency range * Optimum decoupling of input frequency from oscillator * Double balanced mixer with wide dynamic range and low-impedance inputs for the VHF, HYPER and UHF frequency range * Internal band switch * Low-noise reference voltage * Package P-DSO-28-1 1.2 Application The IC is suitable for all tuners in TV and VCR sets. Type TUA 6010X Ordering Code Q67001-A5210 Package P-DSO-28-1 Semiconductor Group 1 05.96 TUA 6010X 1.3 Pin Configuration (top view) P-DSO-28-1 Figure 1 Semiconductor Group 2 05.96 TUA 6010X 1.4 Pin Definitions and Functions Pin No. Symbol Function PLL Section 6 9 10 11 12 13 14 15 16 17 18 19 CAS GNDD SDA SCL Chip address select Ground for digital block (PLL) Data input/output for the I2C Bus Clock input for the I2C Bus Positive supply voltage for digital block (PLL) 4 MHz low-impedance crystal oscillator input 4 MHz low-impedance crystal oscillator input Port output/TTL input Port output/TTL input Open collector output for pull-up resistor/loop filter VVCCD Q Q P1/I1 P0/I0 TUNE P2/ADC Port output/ADC input CHPMP Charge pump output/loop filter Mixer Oscillator Section 1 2 3 4 5 7 8 20 21 22 23 MIXU MIXU MIXV MIXV UHF mixer input, low-impedance, symmetrical to MIXU UHF mixer input, low-impedance, symmetrical to MIXU VHF or HYPER mixer input, low-impedance, symmetrical to MIXV VHF or HYPER mixer input, low-impedance, symmetrical to MIXV Positive supply voltage for analog block Open collector mixer output, high-impedance, symmetrical to IF Open collector mixer output, high-impedance, symmetrical to IF Ground for analog block VHF oscillator amplifier, high-impedance base input, symmetrical to OV-B2 VHF oscillator amplifier, high-impedance collector output, symmetrical to OV-C1 VHF oscillator amplifier, high-impedance collector output, symmetrical to OV-C2 VVCCA IF IF GNDA OV-B1 OV-C2 OV-C1 Semiconductor Group 3 05.96 TUA 6010X 1.4 Pin Definitions and Functions (cont'd) Pin No. Symbol Function 24 25 26 27 28 OV-B2 OU-B1 OU-C2 OU-C1 OU-B2 VHF oscillator amplifier, high-impedance base input, symmetrical to OV-B1 UHF oscillator amplifier, high-impedance base input, symmetrical to OV-B2 UHF oscillator amplifier, high-impedance collector output, symmetrical to OU-C1 UHF oscillator amplifier, high-impedance collector output, symmetrical to OU-C2 UHF oscillator amplifier, high-impedance base input, symmetrical to OU-B1 Semiconductor Group 4 05.96 TUA 6010X 1.5 Functional Block Diagram Figure 2 Block Diagram Semiconductor Group 5 05.96 TUA 6010X 2 Functional Description The TUA 6010X device combines a digitally programmable phase locked loop (PLL), with a mixer oscillator block including two balanced mixers and oscillators for use in TV tuners. The PLL block with four hard-switched chip addresses forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the tuner oscillator up to 1.1 GHz in increments of 62.5 kHz. The tuning process is controlled by a microprocessor via an I2C Bus. The device has three output ports, which all can also be used as input ports (two TTL inputs and one A/D converter input). A flag is set when the loop is locked. The input ports and lock flag can be read by the processor via the I2C Bus. The mixer oscillator block includes two balanced mixers (double balanced mixer with low-impedance input), two frequency and amplitude-stable balanced oscillators for VHF, HYPER and UHF, a low-noise reference voltage source and a band switch. Semiconductor Group 6 05.96 TUA 6010X 3 Circuit Description Mixer-Oscillator Block The mixer oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators for VHF and/or HYPER and UHF, a reference voltage source and a band switch. Filters between tuner input and IC separate the TV frequency signals into two bands. The band switch ensures that only one mixer oscillator block at a time is activated. In the activated band the signal passes a front-end stage with MOSFET amplifier, a double tuned bandpass filter and is then fed to the balanced mixer input of the IC which has a low-impedance input. The input signal is mixed there with the on-chip oscillator signal from the activated oscillator section. PLL Block The mixer oscillator signal VCO/VCO is internally DC coupled as a differential signal at the programmable divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through 32767 and is then compared in a digital frequency/ phase detector to a reference frequency fREF = 62.5 kHz. This frequency is derived from a balanced, low-impedance 4 MHz crystal oscillator (pin Q, Q) divided by Q = 64. The phase detector has two outputs UP and DOWN that drive two current sources I+ and I- of a charge pump. If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the I+ current source pulses for the duration of the phase difference. In the reverse case the I- current source pulses. lf the two signals are in phase, the charge pump output (CHGPMP) goes into the high-impedance state (PLL is locked). An active lowpass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external pull-up resistor at TUNE and external RC circuitry). The charge pump output is also switched into the high-impedance state when the control bit T0 = `1'. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of selfdischarge in the peripheral circuitry. TUNE may be switched off by the control bit OS to allow external adjustments. By means of a control bit 5I the pump current can be switched between two values by software. This programmability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO gains can be compensated, for example. The software-switched ports P0, P1, P2 are general-purpose open-collector outputs.The test bit T1 = `1', switches the test signals fREF (4 MHz/32) and Cy (divided input signal) to P0 and P1 respectively. P0, P1, P2 are bidirectional: P0 and P1 are TTL inputs; P2 is an A/D converter input. Semiconductor Group 7 05.96 TUA 6010X Data are exchanged between the processor and the PLL via the I2C Bus. The clock is generated by the processor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). Both inputs have hysteresis and a lowpass characteristic, which enhance the noise immunity of the I2C Bus. The data from the processor pass through an I2C Bus controller. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are `HIGH'). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes `LOW', while SCL remains `HIGH'. Stop condition: SDA goes `HIGH' while SCL remains `HIGH'. All further information transfer takes place during SCL = `LOW', and the data is forwarded to the control logic on the positive clock edge. The table 1 `bit allocation' should be referred to the following description. All telegrams are transmitted byte by byte, followed by a ninth clock pulse, during which the control logic returns the SDA line to `LOW' (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The eighth bit (R/W) determines whether data are written into (R/W = `0') or read from (R/W = `1') the PLL. In the data portion of the telegram during a WRITE operation, the first bit of the first or third data byte determines whether a divider ratio or control information is to follow. In each case the second byte of the same data type or a stop condition has to follow the first byte. If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the status byte onto the SDA line. lf the processor generates an acknowledge, a further status byte is output; otherwise the data line is released to allow the processor to generate a stop condition. The status word consists of two bits from the TTL input ports, three bits from the A/D converter, the lock flag and the power ON flag. Four different chip addresses can be set by appropriate connection of pin CAU (see table 2 `address selection'). When the supply voltage is applied, a power-on reset circuit prevents the PLL from setting the SDA line to `LOW', which would block the bus. The power-on reset flag POR is set at power-on and when VVCCD goes below 3.2 V. It will be reset at the end of a READ operation. Semiconductor Group 8 05.96 TUA 6010X The lock detector resets the lock flag FL when the width of the charge pump current pulses is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, when FL = `1', the maximum deviation of the input frequency from the programmed frequency is given by f = Ip (KVCO / fQ) (C1 + C2)/(C1 C2) where Ip is the charge pump current, KVCO the VCO gain, fQ the crystal oscillator frequency and C1, C2 the capacitances in the loop filter (see application circuit). As the charge pump pulses at 62.5 kHz (= fREF), it takes a maximum of 16 s for FL to be reset after the loop has lost lock state. Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive fREF periods. Therefore it takes between 128 s and 144 s for FL to be set after the loop regains lock. Table 1 Bit Allocation Read/Write Data MSB Bit6 Write Data Address Byte Prog. Divider Byte 1 Prog. Divider Byte 2 Control Byte 1 Control Byte 2 Read Data Address Byte Status Byte 1 1 0 x 0 I1 0 I0 MA1 A2 MA0 A1 1 A0 Ack Ack 1 0 n7 1 V/U 1 n14 n6 5I x 0 n13 n5 T1 x 0 n12 n4 T0 x 0 n11 n3 1 x MA1 n10 n2 1 P2 MA0 n9 n1 1 P1 0 n8 n0 OS P0 Ack Ack Ack Ack Ack Bit5 Bit4 Bit3 Bit2 Bit1 LSB Ack POR FL Note: MSB is shifted first. Semiconductor Group 9 05.96 TUA 6010X Divider Ratio N = 16384 x n14 + 8192 x n13 + 4096 x n12 + 2048 x n11 + 1024 x n10 + 512 x n9 + 256 x n8 + 128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2 + 2 x n1 + n0 Ports P0, P1, P2 1 0 Open-collector output is active Open-collector output is inactive, TTL-inputs I1,I0 and ADC available Bandswitch V/U `HIGH' switch to OSC/MIX UHF Pump Current 5I `HIGH' switch to high current Disabling Tuning Voltage OS `HIGH' disables TUNE flag is set at power-on and reset at the end of READ operation flag is set when loop is locked input data from pins P1/I1, P0/I0 Power ON Reset Flag POR: PLL Lock Flag FL: TTL-Inputs I1, I0: Semiconductor Group 10 05.96 TUA 6010X Table 2 Address Selection Voltage at CAS (0 ... 0.1) x VVCCD Open circuit (0.4 ... 0.6) x VVCCD (0.9 ... 1) x VVCCD Table 3 Test Modes Test Mode Normal operation P1 = Cy output, P0 = fREF output Charge pump output CHGPMP is in high-impedance state TTL-inputs I1/I0 are Cy/fREF inputs of phase detector Table 4 A/D Converter Levels Voltage at P2/ADC (0 ... 0.15) x VVCCD (0.15 ... 0.3) x VVCCD (0.3 ... 0.45) x VVCCD (0.45 ... 0.6) x VVCCD (0.6 ... 1) x VVCCD A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0 T1 0 1 0 1 T0 0 0 1 1 M1 0 0 1 1 M0 0 1 0 1 Semiconductor Group 11 05.96 TUA 6010X Figure 3 Semiconductor Group 12 05.96 TUA 6010X 4 4.1 Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values min. max. Unit Remarks TA = - 20 C to + 80 C Parameter PLL Supply voltage Current Output CHGPMP Crystall oscillator pins Q, Q Bus input/output SDA Bus input SCL Port outputs P0, P1, P2 Chip address switch CAS Output active filter TUNE Bus output SDA Port outputs P0, P1, P2 Total port output current Junction temperature Storage temperature Thermal resistance (junction to ambient) Mixer Oscillator Supply voltage Current Output IF, IF VVCCD IVCCD VCHGPMP VQ VSDA VSCL VP VCAS VTUNE ISDAL IPL IPL TJ TS RthA - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 -1 -1 6 38 3.5 V mA V V V V V V V mA mA mA C C K/W Open collector Open collector VVCCD 6 6 13 VVCCD 33 5 15 20 125 - 40 125 75 VVCCA IVCCA IIF, IF - 0.3 6 38 9 V mA mA Open collector Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Semiconductor Group 13 05.96 TUA 6010X 4.2 Operating Range Symbol Limit Values min. max. 5.5 5.5 33 33 5.5 8.0 32767 500 900 500 900 80 MHz MHz MHz MHz C V V mA mA V mA Open collector Open collector 4.5 4.5 16 16 4.5 4.0 256 30 400 30 400 - 20 Unit Remarks Parameter Supply voltage Supply current Mixer output voltage Mixer output current Programmable divider factor VHF mixer input frequency range UHF mixer input frequency range VHF oscillator frequency range UHF oscillator frequency range Ambient temperature VVCCD VVCCA IVCCD IVCCA VIF, IF IIF, IF N fMIXV fMIXU fOV fOU TA Note: In the operating range the functions given in the circuit description are fulfilled. Semiconductor Group 14 05.96 TUA 6010X 4.3 AC/DC Characteristics Symbol min. Limit Values typ. max. Unit Test Condition VVCCD = 4.5 V to 5.5 V, TA = - 20 C to 80 C Parameter PLL Supply current IVCCD 19 24 29 mA VVCCD = 5 V Crystal Oscillator Connections Q, Q Crystal frequency Crystal resistance1) Oscillation frequency Input impedance1) fQ RQ fQ 3.2 10 4.0 4.8 100 MHz Series resonance Series resonance 3.99975 4.000 4.00025 MHz t.b.d. - 600 t.b.d. t.b.d. fQ = 4 MHz Drive current1) IQ Arms fQ = 4 MHz dB ZQ - 750 - 900 20 fQ = 4 MHz fQ = 4 MHz Margin aH st from 1 (fundamental) to 2nd and 3rd harmonics1) 1) Design note only: no 100 % final inspection. Semiconductor Group 15 05.96 TUA 6010X 4.3 AC/DC Characteristics (cont'd) Symbol min. Limit Values typ. max. Unit Test Condition VVCCD = 4.5 V to 5.5 V, TA = - 20 C to 80 C Parameter Charge Pump Output CHGPMP (VVCCD = 5 V) HIGH output current LOW output current Tristate current Output voltage ICPH ICPL ICPZ VCP 90 22 220 300 50 1 75 A A nA 5I = `1', VCP = 2 V 5I = `0', VCP = 2 V T0 = `1', VCP = 2 V locked 1.0 2.5 V Drive Output TUNE (open collector) HIGH output current LOW output voltage ITH VTL 10 0.5 A V VTH = 33 V, T0 = `1' ITL = 1.5 mA Port Outputs P0, P1, P2 (open collector) HIGH output current LOW output voltage IPOH VPOL 10 0.5 A V VPOH = 13.5 V IPOL = 15 mA Semiconductor Group 16 05.96 TUA 6010X 4.3 AC/DC Characteristics (cont'd) Symbol min. Limit Values typ. max. Unit Test Condition VVCCD = 4.5 V to 5.5 V, TA = - 20 C to 80 C Parameter TTL Port Inputs P0, P1 HIGH input voltage LOW input voltage HIGH input current LOW input current VPIH VPIL IPIH IPIL 2.7 0.8 10 - 10 V V A A VPIH = 13.5 V VPIL = 0 V ADC Port Input P2 HIGH input current LOW input current IADCH IADCL - 10 10 A A Address Selection Input CAS HIGH input current LOW input current ICASH ICASL - 50 50 A A VCASH = 5 V VCASL = 0 V Semiconductor Group 17 05.96 TUA 6010X 4.3 AC/DC Characteristics (cont'd) Symbol min. Limit Values typ. max. Unit Test Condition VVCCD = 4.5 V to 5.5 V, TA = - 20 C to 80 C Parameter I2C Bus Bus Inputs SCL, SDA HIGH input voltage LOW input voltage HIGH input current LOW input current VIH VIL IIH IIL 3 5.5 1.5 10 V V A A VIH = VS VIL = 0 V - 20 Bus Output SDA (open collector) HIGH output current LOW output voltage IOH VOL 10 0.4 A V VOH = 5.5 V IOL = 3 mA Edge Speed SCL, SDA Rise time Fall time tr tf 300 300 ns ns Clock Timing SCL Frequency HIGH pulse width LOW pulse width fSCL tH tL 0 0.6 1.3 400 kHz s s Semiconductor Group 18 05.96 TUA 6010X 4.3 AC/DC Characteristics (cont'd) Symbol min. Limit Values typ. max. Unit Test Condition VVCCD = 4.5 V to 5.5 V, TA = - 20 C to 80 C Parameter Start Condition Set-up time Hold time tsusta thsta 0.6 0.6 s s Stop Condition Set-up time Bus free Data Transfer Set-up time Hold time Input hysteresis SCL, SDA1) tsusto tbuf 0.6 1.3 s s tsudat thdat Vhys 0.1 0 200 s s mV VN Noise immunity SCL, SDA1), 2) Capacitive load for each bus line 1) 2) 5 Vpp fN = 2 MHz ... 14 MHz CL 400 pF Design note only: no 100 % final inspection. Sinusoidal noise signal applied via a 33 pF coupling capacitor. Semiconductor Group 19 05.96 TUA 6010X 4.3 AC/DC Characteristics Symbol min. Limit Values typ. max. Unit Test Condition VVCCD = 4.5 V to 5.5 V, TA = 25 C Parameter Mixer Oscillator Current consumption Mixer output impedance IVCCA IVCCA RIF, IF CIF, IF 15 18 21 24 20 0.5 27 30 mA mA k pF Bit V/U = `L' Bit V/U = `H' Parallel equivalent circuit Parallel equivalent circuit VHF and HYPER Circuit Section Oscillator frequency range fOSCV fOSCH fOSCV fOSCV 80 140 170 450 400 500 100 MHz MHz kHz kHz kHz dBV dBV dBV dBV Vd = 0 ... 28 V; VHF Vd = 0 ... 28 V; HYP VS = 5 V 10 % T = 25 C Oscillator drift fOSCV t = 5 s up to 15 min after switching on f = 10 kHz in channel E2 f = 10 kHz in channel S10 fint = E2 + N + 5 - 1 MHz fint = S10 + N + 5 - 1 MHz Channel E2 (DSB) Channel 10 (DSB) Oscillator pulling VMIXV VMIXV VMIXV VMIXV GMixV FMixV FMixV VMixV RMixV LMixV aIF 100 100 80 80 11 108 108 88 88 14 5 5 17 8 8 Mixer gain Mixer noise figure Crosstalk fin/LO Mixer input impedance IF suppression dB dB dB 150 1000 20 10 20 mVrms Max. input level for 10 dB distance fin/LO nH dB Serial equivalent circuit Serial equivalent circuit VMixB = 80 dBV Semiconductor Group 20 05.96 TUA 6010X 4.3 AC/DC Characteristics (cont'd) Symbol min. Limit Values typ. max. Unit Test Condition VVCCD = 4.5 V to 5.5 V, TA = 25 C Parameter UHF Circuit Section Oscillator frequency range fOSCU 440 900 MHz Vt = 0 ... 28 V VS = 5 V 10 % T = 25 C Oscillator drift fOSCU fOSCU fOSCU Oscillator pulling 400 800 100 100 100 80 80 11 108 108 88 88 14 6 7 150 1000 20 10 20 17 9 10 kHz kHz kHz BV BV dBV dBV dB dB dB t = 5 s up to 15 min after switching on f = 10 kHz in channel E21 f = 10 kHz in channel E68 fint = E21 + N + 5 - 1 MHz fint = E68 + N + 5 - 1 MHz Channel E21 (DSB) Channel E68 (DSB) VMIXU VMIXU VMIXU VMIXU GMixU FMixU FMixU VMixU RMixU LMixU aIF Mixer gain Mixer noise figure Crosstalk fin/LO Mixer input impedance IF suppression mVrms Max. input level for 10 dB distance fin/LO nH dB Serial circuit equivalent Serial circuit equivalent VMixB = 80 dBV Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Semiconductor Group 21 05.96 TUA 6010X Test Circuit 1 Figure 4 Measurement of Crystal Oscillator Frequency Figure 5 Equivalent I/O-Schematic Semiconductor Group 22 05.96 TUA 6010X Test Circuit 2 Figure 6 Measurement of S-Parameters S11, S12, S21, S22 and Calculation of -Equivalent Circuit Table 5 Test Frequency Test Point Mixer input impedance VHF Mixer input impedance UHF Test Frequency in MHz 300 600 Pin x 3 1 Pin y 4 2 Semiconductor Group 23 05.96 TUA 6010X Test Circuit 3 Figure 7 Measurement of Output Impedance by Measurement of S-Parameters S11, S12, S21, S22 at 45 MHz Semiconductor Group 24 05.96 TUA 6010X Test Circuit 4 Figure 8 Semiconductor Group 25 05.96 TUA 6010X Equivalent I/O-Schematic Figure 9 Equivalent I/O-Schematic of Charge Pump Semiconductor Group 26 05.96 TUA 6010X Figure 10 Equivalent I/O-Schematic of Port Pins Semiconductor Group 27 05.96 TUA 6010X Figure 11 Equivalent I/O-Schematic of CAS Pin Semiconductor Group 28 05.96 TUA 6010X Figure 12 Equivalent I/O-Schematic of SDA/SCL Pins Figure 13 Equivalent I/O-Schematic of MIXU/MIXU/MIXV/MIXV Pins Semiconductor Group 29 05.96 TUA 6010X Figure 14 Equivalent I/O-Schematic of UHF- VHF-Oscillator Pins Semiconductor Group 30 05.96 TUA 6010X Figure 15 I2C Bus Timing Semiconductor Group 31 05.96 TUA 6010X 5 Package Outlines P-DSO-28-1 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 32 Dimensions in mm 05.96 GPS05123 |
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